1. Field of the Invention
This invention relates to the field of digital systems, such as personal computers and digital cameras, employing nonvolatile memory as mass storage, for use in replacing hard disk storage or conventional film. More particularly, this invention relates to an architecture for increasing the performance of such digital systems by increasing the rate at which digital information is read from and written to the nonvolatile memory.
2. Description of the Prior Art
With the advent of higher capacity solid state storage devices (nonvolatile memory), such as flash or EEPROM memory, many digital systems have replaced conventional mass storage devices with flash and/or EEPROM memory devices. For example, personal computers (PCs) use solid state storage devices for mass storage purposes in place of conventional hard disks. Digital cameras employ solid state storage devices in cards to replace conventional films.
FIG. 1 shows a prior art memory system 10 including a controller 12, which is generally a semiconductor (or integrated circuit) device, coupled to a host 14 which may be a PC or a digital camera. The controller 12 is further coupled to a nonvolatile memory bank 16. Host 14 writes and reads information, organized in sectors, to and from memory bank 16 which includes a first nonvolatile memory chip 18 and a second nonvolatile memory chip 20. Chip 18 includes: an I/O register 22 having a port 24 connected to a port 26 of controller 12 via a first bus 28 which includes 8 bit lines; and a storage area 30 coupled with I/O register 22. Chip 20 includes: an I/O register 32 having a port 34 connected to a port 36 of controller 12 via a second bus 38 which includes 8 bit lines; and a storage area 40 coupled with I/O register 32. The first and second buses 28, 38 are used to transmit data, address, and command signals between the controller and the memory chips 18 and 20. The least significant 8 bits (LSBs) of 16 bits of information are provided to chip 18 via the first bus 28, and the most significant 8 bits (MSBs) are provided to the chip 20 via the second bus 38.
Memory bank 16 includes a plurality of block locations 42 each of which includes a plurality of memory row locations. Each block location of the memory bank is comprised of a first sub-block 44 located in the first non-volatile memory chip, and a corresponding second sub-block 46 located in the second non-volatile memory chip. Each memory row location includes a first row-portion 48 and a corresponding second row-portion 50. In the depicted embodiment each of the first and second row-portions 48 and 50 includes storage for 256 bytes of data information plus an additional 8 bytes of storage space for overhead information. Where a sector includes 512 bytes of user data and 16 bytes of non-user data (the latter commonly referred to as overhead information), 256 bytes of the user data and 8 bytes of the overhead information of the sector may be maintained in the first row portion 48 of chip 18 and the remaining 256 bytes of user data and remaining 8 bytes of overhead information of the same sector may be maintained in the second row portion 50 of chip 20. Thus, half of a sector is stored in a memory row location 48 of chip 18 and the other half of the sector is stored in memory row location 50 of chip 20. Additionally, half of the overhead information of each stored sector is maintained by chip 18 and the other half by chip 20.
In general, reading and writing data to flash memory chips 18 and 20 is time consuming. Writing data to the flash memory chips is particularly time consuming because data must be latched in I/O registers 22 and 32, which are loaded 1 byte at a time via the first and second buses, and then transferred from the I/O registers 22 and 32 to the memory cells of the flash memory chips 18 and 20 respectively. The time required to transfer data from the I/O registers to memory, per byte of data, is proportional to the size of the I/O registers and the size of the flash memory chip.
During a write operation, controller 12 writes a single sector of information to memory bank 16 by: (1) transmitting a write command signal to each of chips 18 and 20 via buses 28 and 38 simultaneously; (2) transmitting address data to chips 18 and 20 specifying corresponding sub-blocks 44 and 46 of the chips via buses 28 and 38 simultaneously; and (3) sequentially transmitting a byte of user data to each of chips 18 and 20 via buses 28 and 38 simultaneously for storage in the corresponding sub-blocks 44 and 46. The problem with such prior art systems is that while two bytes of information are written and read at a time, only one sector of information is accommodated at a time by the memory bank 16 during a write command initiated by the host 14.
Another prior art digital system 60 is shown in FIG. 2 to include a controller 62 coupled to a host 64, and a nonvolatile memory bank 66 for storing and reading information organized in sectors to and from nonvolatile memory chip 68, included in the memory bank 66. While not shown, more chips may be included in the memory bank, although the controller, upon command by the host, stores an entire sector in one chip. A block, such as block 0, includes 16 sectors S0, S1, . . . , S15. Also included in the chip 68 is an I/O register 70, which includes 512 bytes plus 16 bytes, a total of 528 bytes, of storage space. The controller transfers information between host 64 and memory 66 a byte at-a-time. A sector of 512 bytes of user data plus 16 bytes of overhead information is temporarily stored in the I/O register during a write operation and then transferred to one of the blocks within the memory device for storage thereof. During a read operation, a sector of information is read from one of the blocks of the memory device and then stored in the I/O register for transfer to the controller. An important problem with the prior art architecture of FIG. 2 is that while a total of 528 bytes may be stored in the I/O register 36, only one byte of sector information may be transferred at a time between the controller and the memory bank thereby impeding the overall performance of the system.
Both of the prior art systems of FIGS. 1 and 2 maintain LBA to PBA mapping information for translating a host-provided logical block address (LBA) identifying a sector of information to a physical block address (PBA) identifying the location of a sector within the memory bank. This mapping information may generally be included in volatile memory, such as a RAM, within the controller, although it may be maintained outside of the controller.
FIG. 3 shows a table diagram illustrating an example of an LBA-PBA map 300 defined by rows and columns, with each row 302 being uniquely identified, addressed, by a value equal to that of the LBA received from the host divided by 16. The row numbers of FIG. 3 are shown using hexadecimal notation. Thus, for example, row 10H (in Hex.) has an address value equal to 16 in decimal. Each row 302 of map 300, includes a storage location field 304 for maintaining a virtual PBA value, an xe2x80x98oldxe2x80x99 flag field 306, a xe2x80x98usedxe2x80x99 flag field 308, and a xe2x80x98defectxe2x80x99 flag field 310. The flag fields provide information relating to the status of a block of information maintained within the memory bank (in FIGS. 1 and 2). The virtual PBA field 304 stores information regarding the location of the block within the memory bank.
FIG. 4 shows a table diagram illustrating an exemplary format for storage of a sector of data maintained in a memory bank. The virtual PBA field 304 (FIG. 3) provides information regarding the location of a block 400 of information with each block having a plurality of sectors 402. Each sector 402 is comprised of a user data field 404, an ECC field 406, an xe2x80x98oldxe2x80x99 flag field 408, a xe2x80x98usedxe2x80x99 flag field 410 and a xe2x80x98defectxe2x80x99 flag field 412.
A further problem associated with prior art systems of the kind discussed herein is that the table 300 (in FIG. 3) occupies much xe2x80x98real estatexe2x80x99 and since it is commonly comprised of RAM technology, which is in itself costly and generally kept within the controller, there is substantial costs associated with its manufacturing. Furthermore, as each row of table 300 is associated with one block of information, the larger the number of blocks of information, the larger the size of the table, which is yet an additional cost for manufacturing the controller and therefore the digital system employing such a table.
What is needed is a digital system employing nonvolatile memory for storage of digital information organized in sector format for reducing the time associated with performing reading and writing operations on the sectors of information thereby increasing the overall performance of the system while reducing the costs of manufacturing the digital system.
It is an object of the present invention to increase the performance of a digital system having a controller coupled to a host for operating a nonvolatile memory bank including one or more nonvolatile memory devices, such as flash and/or EEPROM chips, by reducing the time associated with reading and writing information to the nonvolatile memory bank.
It is another object of the present invention, as described herein, to decrease the time associated with storing sectors of information by writing at least two sectors of information to at least two nonvolatile memory semiconductor devices during a single write command initiated by the host.
It is another object of the present invention as described herein to decrease the time associated with reading sectors of information by reading at least two sectors of information from at least two nonvolatile memory semiconductor devices during a single read command initiated by the host.
It is a further object of the present invention to store overhead information associated with two sectors of information in one of the two nonvolatile memory semiconductor devices.
It is yet another object of the present invention to simultaneously access two bytes of a sector of information stored within two nonvolatile memory devices thereby increasing the rate of performance of a system employing the present invention by an order of magnitude of at least two.
It is yet another object of the present invention to access one byte of a first sector and one byte of a second sector of information simultaneously within two nonvolatile memory devices thereby increasing the rate of performance of a system employing the present invention.
It is a further object of the present invention to reduce the size of a volatile memory table, or map, that maintains translations between the host-provided sector addresses to addresses of blocks within the nonvolatile memory devices thereby reducing the cost of manufacturing the digital system.
Briefly, the present invention includes a digital system having a controller semiconductor device coupled to a host and a nonvolatile memory bank including a plurality of nonvolatile memory devices. The controller transfers information, organized in sectors, with each sector including a user data portion and an overhead portion, between the host and the nonvolatile memory bank and stores and reads two bytes of information relating to the same sector simultaneously within two nonvolatile memory devices. Each nonvolatile memory device is defined by a row of memory locations wherein corresponding rows of at least two semiconductor devices maintain two sectors of information therein with the overhead information relating to the two sectors maintained in one of the memory rows of the nonvolatile memory device. Each 32 sectors of information defines a block identified by a virtual physical block address with a block of information expanding between two memory devices wherein an even and an odd byte of a sector is simultaneously read from or written to two nonvolatile memory devices. In another embodiment, the controller stores an entire sector of information within a single nonvolatile memory device and reads from or writes to, a sector of information by processing corresponding bytes of at least two sectors in two nonvolatile memory devices simultaneously.
These and other objects and advantages of the present invention will no doubt become apparent to those skilled in the art after having read the following detailed description of the preferred embodiments illustrated in the several figures of the drawing.